A memory cell of typical DRAM is mainly composed of a transistor, which has a gate, a source, and a drain, and a capacitor. To reduce the area used for capacitors and to increase capacitivity, trench capacitors have been extensively used in DRAM design.
FIG. 1A illustrates a schematic cross-sectional view of prior art DRAM memory cells using trench capacitors, wherein it comprises a substrate 100, trench capacitor electrodes 101A and 101B (only the upper parts are shown), a source 102, drains 103A and 103B, a bit line contact structure 104, and gates 105A and 105B. Thus two memory cells are that formed (one is on the left side and the other is on the right side) and share source 102, and bit line contact structure 104 is formed between the two gates 105A and 105B. Bit line contact structure 104 additionally connects to a bit line (not shown) and gates 105A and 105B furthermore connects to a word line (not shown), respectively, wherein said bit line is constructed in a upper structure and parallel to the direction that said two memory cells disposed; said word line is constructed in another upper structure and perpendicular to said bit line. During the operation, when apply voltage onto the related bit line and word line to access the memory cell on the right side, the current flows through bit line contact structure 104, source 102, gate channel 108, drain 103B, and then enters into capacitor electrode 101B, shown as current direction 107.
Nevertheless, because the size of integrated circuit components continues decreasing, thereby the length of transistor gate channel is becoming shorter, which can easily cause the occurrences of short channel effects such as drop in threshold voltage and increase in current leakage from drain to source, etc. Therefore in order to improve this problem the design of elongated channel transistor gate with a recess has been developed in prior arts. As illustrated in FIG. 1B, in which it comprises substrate 110, trench capacitor electrodes 111A and 111B (only upper parts are shown), source 112, drains 113A and 113B, bit line contact structure 114, and gates 115A and 115B. Gates 115A and 115B respectively have recesses 116A and 116B formed in substrate 110, thereby channels 117A and 117B formed along recesses 116A and 116B during the operation have longer lengths.
Usually the location of transistor gate is defined by photolithography, which aligns and transfers the patterns on the mask to the thin film layer or the silicon under photoresist then further produces the gate. However, as the component size continues decreasing, the problem related to overlay error between multiple layers in photolithography is becoming serious, and it is thus more unlikely to produce gates by accurately defining the location of the reducing size of transistor gate using photolithography technique. Thus, a method is needed for a solution to overcome the problems stated above.